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dpacc

Project: Data Plane Acceleration (DPACC)

As a result of convergence of various traffic types and increasing data rates, the performance requirements (both in terms of bandwidth and real-time-ness) on data plane devices within network infrastructure have been growing at significantly higher rates than in the past. As the traditional ‘bump-in-the-wire’ network functions evolve to a virtualized paradigm with NFV, the focus will be even higher to deliver high performance within very competitive cost envelopes. At the same time, application developers have, in some cases, taken advantage of various hardware and software acceleration capabilities, many of which are platform supplier dependent. There is a clear impetus to move away from proprietary data plane interfaces, in favor of more standardized interfaces to leveraging the data plane capability of underlying platforms – whether using specialized hardware accelerators or general purpose CPUs.

The goal of this project is to specify a general framework for VNF data plane acceleration (or DPA for short), including a common suite of abstract APIs at various OPNFV interfaces, to enable VNF portability and resource management across various underlying integrated SOCs that may include hardware accelerators or standard high volume (or SHV) server platforms that may include attached hardware accelerators. It may be desirable, as a design choice in some cases,that such DPA API framework could easily fit underneath existing prevalent APIs (e.g. sockets) – mainly for legacy implementations even though they may not be most performance efficient. But this project should not seek to dictate what APIs an application must use, rather recognizing that API abstraction is likely a layered approach and developers can decide which layer to access directly, depending on the design choice for a given application usage.

The overall project plan for DPACC is:

  • Phase 1: (by 2015Q2)
    1. document typical VNF use-cases and high-level requirements for the generic functional abstraction for high performance data plane and acceleration functions, including hardware and software acceleration; and
    2. identify the potential extensions across various NFV interfaces and evaluate current state-of-art solutions from open-source upstream projects according to identified requirements and targeted framework.
  • Phase 2: (by 2015Q4)
    1. specify detailed framework/API design/choice and document test cases for selected use-cases;
    2. provide open source implementation for both the framework and test tools;
    3. coordinate integrated testing and release testing results; and
    4. interface specification.

Related wiki pages:


Key Project Facts

Project Creation Date: February 10, 2015
Project Category: Requirement
Lifecycle State: Incubation
Primary Contact: Linli Deng (denglingli@chinamobile.com)
Project Lead: Lingli Deng (denglingli@chinamobile.com)

Committers:

  • Lingli Deng (China Mobile, denglingli@chinamobile.com)
  • Ola Liljedahl (ARM, Ola.Liljedahl@arm.com)
  • Kin-Yip Liu (Cavium, Kin-Yip.Liu@caviumnetworks.com)
  • Xinyu Hu (Huawei, huxinyu@huawei.com)
  • Vincent Jardin (6WIND, vincent.jardin@6wind.com)
  • Wenjing Chu (DELL, Wenjing_Chu@DELL.com)
  • Bin Hu (AT&T, bh526r@att.com)
  • Subhashini Venkataraman (Freescale, subhaav@freescale.com)
  • Leon Wang (Altera, ALEWANG@altera.com)
  • Keith Wiles (Intel, Keith.wiles@intel.com)
  • Xiaowei Ji (ZTE, ji.xiaowei@zte.com.cn)

Contributors:

  • Bob Monkman (ARM, Bob.Monkman@arm.com)
  • Peter Willis (British Telecom, peter.j.willis@bt.com)
  • Fahd Abidi (Xilinx, fahd.abidi@xilinx.com)
  • Cyril Chemparathy (EZchip, cchemparathy@ezchip.com)
  • Deepak Unnikrishnan (Altera, deepak.cu@gmail.com)
  • Julien Zhang (ZTE, zhang.jun3g@zte.com.cn)
  • Srini Addepalli (Intel, srinivasa.r.addepalli@intel.com)
  • François-Frédéric Ozog (6WIND, ff.ozog@6wind.com)
  • Tapio Tallgren (Nokia, tapio.tallgren@nsn.com)
  • Mikko Ruotsalainen (Nokia, mikko.ruotsalainen@nsn.com)
  • Zhipeng Huang (Huawei, huangzhipeng@huawei.com)
  • Rabi Abdel (Altera, ahmrabi@altera.com)
  • Venky Venkatesan (Intel, Venky.Venkatesan@intel.com)
  • Alex Mui (ASTRI, alexmui@astri.org)
  • Jesse Ai (ASTRI, jesseai@astri.org)
  • Arashmid Akhavain (Huawei, arashmid.akhavain@huawei.com)
  • Parviz Yegani (Juniper, pyegani@juniper.net)
  • Mario Cho (hephaex@gmail.com)
  • Hongyue Sun (ZTE, sun.hongyue@zte.com.cn)
  • Haishu Zheng (ZTE, zheng.haishu@zte.com.cn)
  • Varun Sethi (Freescale, Varun.Sethi@freescale.com)
  • Bharat Mota (Freescale, bharat.mota@freescale.com)
  • Paul Kangil Choi (ETRI, forerunner@etri.re.kr)
  • John Bromhead (Cavium, John.Bromhead@caviumnetworks.com)
  • Michele Paolino (Virtual Open Systems, m.paolino@virtualopensystems.com)

IRC : freenode.net #opnfv-dpacc (http://webchat.freenode.net/?channels=opnfv-dpacc)
Trello : DPACC trello board for coordination (https://trello.com/b/hfu1Ikk4/dpacc)
Mailing List : no dedicated mailing list - use opnfv-tech-discuss and tag your emails with [dpacc] in the subject for easier filtering
Meetings :

Repository: dpacc

dpacc.txt · Last modified: 2016/02/09 13:48 by Michele Paolino